Field of the Invention
The present invention relates to a programmable read-only memory, and to a method for operating the programmable read-only memory.
Programmable read-only memories or non-volatile memories are known in a multiplicity of embodiments, such as, for example PROMs, EPROMs, EEPROMs and do not require any further explanation. Such memories may be embodied as data memories or as program memories. In particular, the read-only memories which are embodied as EEPROMs can be programmed and erased, but the maximum number of possible write/erase cyclesxe2x80x94referred to as endurancexe2x80x94is upwardly limited and depends in particular on the type of read-only memory.
Flash memories are read-only memories, which are distinguished by particularly simple and high-speed write/erase operations. In flash memories, the memory cells can be programmed electrically either individually or on a segment basis, but a flash memory can only be erased on a segment basis or only in its entirety. The erase operation is carried out by a short electrical erase pulse.
Flash memories are distinguished by a very low supply voltage and low power loss and are thus suitable in particular in systems with a local voltage supply, such as, for example, in a mobile telephone or portable audio appliance.
The demands placed on flash data memories are, in contrast to flash program memories, characterized by a significantly higher endurance and higher selectivity during programming and erasure. In addition, data memories are generally smaller than program memories.
In order to be able to meet the high demands in terms of the highest possible endurance, flash data memories are typically programmed and erased by what is referred to as Fowler-Nordheim tunneling because this method ensures lower and more homogeneous loading of the individual memory cells and their tunnel oxide, as is the case, for example, by programming with hot electrons (channel hot electrons). The thickness of the tunnel oxide in such memory cells is comparatively small, as a result of which it is possible to keep the necessary voltages comparatively low and the necessary times comparatively short during programming and erasure.
However, in particular flash memories, which are programmed and erased by Fowler-Nordheim tunneling are characterized by a comparatively high number of random memory defects such as what are referred to as erratic bits and moving bits, for example. Erratic bits are memory cells, which react differently to the same electrical stress, as a result of which memory faults can arise directly after programming. Moving bits are memory cells which lose their stored charge in a relatively short time, as a result of which the memory cells change their logic state over time. Both memory defects are however not reproducible and occur randomly.
Typical test programs on the wafer and module level for ensuring the quality and reliability of the memory are, however, are suitable only for reproducible memory defects. Memory cells, which are temporarily defective, such as erratic bits and moving bits, cannot be detected, or can only be detected randomly by the filters installed in the test programs.
A possible way of countering this type of fault is to use intelligent methods for detecting and correcting such defects. These methods employ comprehensive coding algorithms, such as, for example the Hamming Code, in which the respective code is stored in additional memory cells. It is very costly to evaluate the coded information because it requires additional evaluation circuitry as well as an additive logic circuit for write/read access operations.
It is accordingly an object of the invention to provide a programmable read-only memory and a method for operating the read-only memory which overcome the above-mentioned disadvantages of the prior art devices and methods of this general type, in which random memory defects can be reliably detected with minimum expenditure and can, if appropriate, be corrected.
With the foregoing and other objects in view there is provided, in accordance with the invention, a programmable read-only memory. The memory contains at least one memory cell array having a multiplicity of memory cells, a multiplicity of memory segments composed of the memory cells and in which data and program parts can be stored, and a multiplicity of redundant memory segments composed of the memory cells and each associated with at least one of the memory segments. In each case one of the memory segments and associated redundant memory segments together form a memory block in which the memory segment and the associated redundant memory segments have the same data content. The memory segment and the associated redundant memory segments of the memory block can be read, erased and/or written to simultaneously.
The read-only memory according to the invention with redundancy is distinguished in that the data and program parts to be stored are stored at least in duplicate. As a result, random defects can easily be detected and corrected. A minimum additional degree of outlay on circuitry is advantageously necessary for the redundancy concept because essentially an analog multiplexer and the corresponding redundant memory segments are necessary. Owing to the fact that just one single sense amplifier is necessary for all memory segments of a memory block, no additional current consumption occurs during the reading and writing. Furthermore, the fact that the memory segments of a memory block are read and written to in parallel results in that there are virtually no negative effects on the speed during write/read access operations.
In one preferred embodiment of the read-only memory, it has double redundancy, i.e. one memory segment and two redundant memory segments are provided per memory block. A read-only memory with double redundancy makes it possible to detect a maximum of two memory defects per memory segment. The double redundancy thus generally constitutes a good compromise in terms of the demands that random memory defects should be detected and corrected in a defined way and yet the additional area required for the redundant memory segments should not become too large. Of course, a lower degree of redundancy or a redundancy greater than two would also be conceivable. In particular, the latter case is advantageous if the data content of a memory segment is very large.
The read-only memory according to the invention is organized in segments, i.e. in each case one memory segment has a relatively large number of memory cells. All the memory segments of the read-only memory typically each have the same data length, for example one byte, one word or one double word.
In a further advantageous refinement, the read-only memory according to the invention has two operating modes. The normal read/write operating mode in which all the memory segments of a memory block are read, written to or erased simultaneously, and the test operating mode in which in each case a single memory segment of a memory block is read, written to or erased. For this purpose, a multiplexer circuit is provided which respectively selects one of the two operating modes. A sense amplifier circuit which is connected downstream of the multiplexer circuit is also adapted to the two operating modes, i.e. it has a corresponding reference level for each of the operating modes.
It is particularly advantageous if the aforesaid sense amplifier circuit has reference levels which can be adjusted in such a way that it is possible to distinguish whether the random defects to be expected occur predominantly as logic xe2x80x9c0xe2x80x9d, as logic xe2x80x9c1xe2x80x9d or as both logic xe2x80x9c0xe2x80x9d and logic xe2x80x9c1xe2x80x9d.
The invention is suitable, in particular in programmable read-only memories, which are embodied as flash memories. Moreover, the invention is particularly advantageous in such flash memories, which are programmed and/or erased by Fowler-Nordheim tunneling because, owing to the lower programming voltage, they typically have a higher random defect density than flash memories, which are programmed by xe2x80x9chot electronsxe2x80x9d. The present invention is however not exclusively restricted to flash memories but can also be used very advantageously in other programmable read-only memories, such as EPROMs or PROMs, for example.
Moreover, the present invention is particularly advantageous in data memories because they are characterized, in comparison with customary program memories, by a relatively high endurance and are thus particularly susceptible to the abovementioned random memory defects.
In accordance with an added feature of the invention, a selection circuit and write/read paths are provided. Each of the write/read paths is connected between one of the memory segment and the associated redundant memory segments of the memory block to the selection circuit. The write/read paths are disposed in parallel with one another.
In accordance with an additional feature of the invention, the selection circuit is a multiplexer through which, in a first operating mode, a single one of the memory segment and the associated redundant memory segments of the memory block can be read, written to or erased. And through the multiplexer, in a second operating mode, all of the memory segment and the associated redundant memory segments of the memory block can be simultaneously read, written to or erased.
In accordance with a further feature of the invention, a sense amplifier circuit is provided and during a read operating mode, the sense amplifier circuit is connected to the selection circuit. The sense amplifier circuit is suitable for reading a single one or all of the memory segment and the associated redundant memory segments of the memory block and the sense amplifier circuit has, for this purpose, at least two different reference levels.
In accordance with another feature of the invention, the at least two different reference levels of the sense amplifier circuit are adjustable depending on whether defects occurring during a writing to, erasure or reading of the memory cells occur predominantly as logic xe2x80x9c1xe2x80x9d, as logic xe2x80x9c0xe2x80x9d or as both logic xe2x80x9c1xe2x80x9d and logic xe2x80x9c0xe2x80x9d.
In accordance with a further added feature of the invention, the memory segment and the associated redundant memory segments have equivalent bit lengths, and the memory segment of the memory block is assigned precisely two of the redundant memory segments.
In accordance with a further additional feature of the invention, the memory cell array is an integrated data memory.
In accordance with another further feature of the invention, the read-only memory is a flash memory, which can be programmed and erased by use of Fowler-Nordheim tunneling.
With the foregoing and other objects in view there is further provided, in accordance with the invention, a method for operating a read-only memory containing at least one memory cell array having a multiplicity of memory cells, a multiplicity of memory segments composed of the memory cells and in which data and program parts can be stored, and a multiplicity of redundant memory segments composed of the memory cells and each associated with at least one of the memory segments. In each case one of the memory segments and associated redundant memory segments together form a memory block. The method includes the steps of providing the read-only memory with a first operating mode and a second operating for performing a read operation, a programming operation, and an erasing operation. In the first operating mode, a selection circuit simultaneously accesses both the memory segment and all of the associated redundant memory segments of the memory block through one write/read path in each case. The selection circuit accesses an individual one of the memory segment and the associated redundant memory segment of the memory block through the write/read path in the second operating mode.
In accordance with an added mode of the invention, there is the step of during a read operation, providing a sense amplifier circuit, which is supplied, in the first operating mode, with a sum of cell currents of both the memory segment and the associate redundant memory segments of the memory block through the selection circuit. The sense amplifier circuit generates a data output signal therefrom and in dependence on a first reference level. The sense amplifier is supplied, in the second operating mode, with a single cell current of an individual one of the memory segment and the associated redundant memory segments through the selection circuit. The sense amplifier circuit generates the data output signal therefrom and in dependence on a second reference level.
In accordance with a concomitant mode of the invention, there is the step of connecting or disconnecting reference elements to/from the sense amplifier circuit in dependence on whether defects generated during writing, erasure or reading occur predominantly as logic xe2x80x9c1xe2x80x9d, as logic xe2x80x9c0xe2x80x9d, or as both logic xe2x80x9c1xe2x80x9d and logic xe2x80x9c0xe2x80x9d. As a result, the first reference level is adapted, by changing it, to the defects that occur.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a programmable read-only memory and a method for operating the read-only memory, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.